1. Field of the Invention
The present invention relates to a Liquid-Crystal Display (LCD) device with Thin-Film Transistors (TFTs) and a method of fabricating the same. More particularly, the invention relates to a LCD device having wiring or interconnection lines made of aluminum (Al) or Al alloy and a layer or layers (a transparent conductive layer or layers) made of a transparent conductive material such as Indium Tin Oxide (ITO) electrically connected to the interconnection lines, and a method of fabricating the LCD device.
2. Description of the Related Art
In recent years, the LCD device has been extensively used as high-resolution displays. Generally, the LCD device comprises a substrate on which switching elements such as TFTs are arranged, which may be termed a “TFT substrates” below; an opposite substrate on which a color filter, a black matrix or the like are formed; and a liquid crystal layer located between the TFT substrate and the opposite substrate. The amount of transmitting light in the respective pixels is controlled by changing the alignment direction of the liquid-crystal molecules with the electric field generated between the electrodes on the TFT substrate and those on the opposite substrate or between the electrodes on the TFT substrate, thereby displaying images on the screen of the LCD device. On the TFT substrate, various wiring or interconnection lines such as gate electrode lines (i.e., scanning lines), drain electrode lines (i.e., signal lines), and common electrode lines are formed in a matrix array. At the ends of these interconnection lines, gate electrode input terminals, drain electrode input terminals, and common electrode input terminals, or the like are formed. These interconnection lines are electrically connected to external driver circuit elements with these terminals. The external driver circuit elements are attached to the TFT substrate by the known TAB (Tape Automated Bonding) method or the like.
With the LCD device having the above-described configuration, the length of the above-described interconnection lines increases as the device enlarges and therefore, their electric resistance (which may be simply termed “resistance” below) increases. Since the resistance increase of the said interconnection lines causes transmission delay of electric signals, the display quality degradation is likely to arise. Moreover, higher density and higher aperture ratio are required for the recent LCD device and thus, the said lines need to be narrowed. If the said lines are narrowed, however, their resistance will increase and thus, the display quality will degrade due to the transmission delay of signals. Accordingly, conventionally, Al has been used to form the said lines, because Al is one of the known low-resistance interconnection materials.
However, the standard electrode potential of Al is largely apart from that of a typical transparent conductive material (e.g., ITO) to be used for the pixel electrodes or the like. Therefore, there is a problem that corrosion is likely to occur in the transparent conductive material due to electrochemical reaction caused by the developing or etching solution used for patterning the transparent conductive layer. In addition, when an Al layer and a transparent conductive material are directly connected to each other, oxygen (O) atoms are likely to be drawn out of the transparent conductive material. In this case, an aluminum oxide (Al2O3) layer with an insulating property is formed at the interface between the Al layer and the transparent conductive material, arising another problem that the contact resistance between them increases.
To solve the above-described two problems, i.e., “corrosion of the transparent conductive layer” and “contact resistance increase at the interface”, conventionally, the following two-layered and three-layered structures have been developed and disclosed for the interconnection lines.
The conventional two-layered structure of the interconnection line comprises an Al layer and a conductive barrier layer (an upper barrier layer) made of tungsten (W) or the like stacked on the Al layer. The conventional three-layered structure of the interconnection line comprises an Al layer, a conductive barrier layer (an upper barrier layer) made of W or the like stacked on the Al layer, and another conductive layer (a lower barrier layer) made of W or the like stacked beneath the Al layer. An example of the interconnection line including the two- and three-layered structures is shown in FIG. 1.
FIG. 1 schematically shows the configuration of a conventional LCD device with TFTs. In FIG. 1, the structures of a transistor section including one of the TFTs, the terminal section of a gate electrode line (i.e., a gate terminal section) connected to the gate electrode of the TFT, and a terminal section of a drain electrode line (i.e., a drain terminal section) connected to the drain electrode of the TFT are shown.
As shown in FIG. 1, gate electrodes 121 and gate electrode lines 122 are formed on a glass plate 101. Each of the gate electrodes 121 is formed by a patterned Al alloy layer 102 and a patterned upper barrier metal layer 111 stacked thereon to have a two-layer structure. Each of the gate electrode lines 122 has the same two-layer structure as the gate electrode 121. The gate electrode lines 122, which are united with the corresponding gate electrodes 121, extend to the corresponding gate terminal sections. The gate electrodes 121 and the gate electrode lines 122 are covered with a gate insulating layer 103 that covers the whole surface of the glass plate 101. The gate insulating layer 103 comprises contact holes 133 in the respective gate terminal sections to expose corresponding parts of the underlying gate electrode lines 122.
In each of the transistor sections, an island-shaped amorphous silicon layer (which will be abbreviated as an “a-Si layer” below) 104 is formed on the gate insulating layer 103 so as to overlap with each of the gate electrodes 121. The a-Si layer 104 is a conductive layer to generate a channel therein. A pair of island-shaped, n+-type a-Si layers 105a and 105b are formed on the a-Si layer 104 to be apart from each other at a predetermined distance. A source electrode 123 and a drain electrode 124 are formed on the n+-type a-Si layers 105a and 105b, respectively. The n+-type a-Si layers 105a and 105b are conductive layers for improving the ohmic contact of the overlying source and drain electrodes 123 and 124 with the underlying a-Si layer 104. The source and drain electrodes 123 and 124 are located on the gate insulating layer 103 in the areas excluding the positions superposed on the n+-type a-Si layers 105a and 105b. 
The source electrode 123 has a three-level or three-layer structure comprising a patterned lower barrier metal layer 106, a patterned Al alloy layer 107 stacked on the lower barrier metal layer 106, and a patterned upper barrier metal layer 112 stacked on the Al alloy layer 107. The drain electrode 124 has the same three-layer structure as the source electrode 123. The drain electrode lines 125, which are formed on the gate insulating layer 103, have the same three-layer structure as the drain electrode 124.
The source electrodes 123, the drain electrodes 124, and the drain electrode lines 125 are covered with a passivation insulating layer 108 formed over the whole surface of the glass plate 101. The passivation insulating layer 108 enters the respective gaps between the source electrodes 123 and the corresponding drain electrodes 124.
Transparent conductive layers 110a, 110b, and 110c, which are formed by a patterned ITO layer, are located on the passivation insulating layer 108. These layers 110a, 110b, and 110c are respectively contacted with the underlying drain electrode 124, the underlying gate electrode line 122, and the underlying drain electrode line 125 by way of the corresponding contact holes penetrating through the passivation insulating layer 108 and/or the gate insulating layer 103.
Specifically, the transparent conductive layer 110a located in each of the transistor sections is in contact with the upper barrier metal layer 112 constituting the upper part of the corresponding drain electrode 124 by way of the corresponding contact hole 131 of the passivation insulating layer 108. The transparent conductive layer 110b located in each of the gate terminal sections is in contact with the upper barrier metal layer 112 constituting the upper part of the corresponding gate electrode line 122 by way of the corresponding contact hole 132 of the passivation insulating layer 108 and the corresponding contact hole 133 of the gate insulating layer 103. The transparent conductive layer 110c located in each of the drain terminal sections is in contact with the upper barrier metal layer 112 constituting the upper part of the corresponding drain electrode line 125 by way of the corresponding contact hole 134 of the passivation insulating layer 108.
As explained above, with the conventional interconnection structure shown in FIG. 1, the transparent conductive layers 110a, 110b, and 110c are not in direct contact with the Al alloy layer 107 of the drain electrode 124, the Al alloy layer 102 of the gate electrode line 122, and the Al alloy layer 107 of the drain electrode line 125. Therefore, electrochemical reaction due to the developing or etching solution in the patterning process of the ITO layer for forming the transparent conductive layers 110a, 110b, and 110c is suppressed. Moreover, since the upper barrier metal layer 111 or 112 intervenes between the transparent conductive layers 110a, 110b, and 110c and the corresponding Al alloy layer 102 or 107, the contact resistance between the layers 110a, 110b, and 110c and the corresponding layer 102 or 107 does not increase.
However, the above-described conventional structure of the interconnection lines has several disadvantages. These disadvantages for the conventional three-layer structure are the same as those for the conventional two-layer structure and therefore, only those for the conventional two-layer structure will be referred to in the following explanation.
The first disadvantage is the step coverage degradation of an overlying layer or layers located on or over the interconnection lines. With the conventional two-layer structure, since the upper barrier metal layer 111 or 112 is stacked on the Al alloy layer 102 or 107, the thickness of the gate electrode lines 122 and the drain electrode lines 125 (i.e., interconnection lines) increases by a value corresponding to the thickness of the upper barrier metal layer 111 or 112. As a result, the step coverage of an overlying layer or layers located on or over the gate electrode lines 122 and the drain electrode lines 125 will degrade.
The second disadvantage is the possibility that the step coverage of an overlying layer or layers located on or over the interconnection lines degrades conspicuously. With the conventional two-layer structure, when the upper barrier metal layer 111 or 112 and the Al alloy layer 102 or 107 are subject to wet etching in a lump to form the said two-layer structure, the Al alloy layer 102 or 107 alone are side-etched. Therefore, undercut portions are formed under the upper barrier metal layer 111 or 112. Due to the undercut portions, the step coverage of the overlying layer or layers may deteriorate.
The third disadvantage is the productivity reduction and fabrication cost increase. With the conventional two-layer structure, to form the upper barrier metal layer 111 or 112, a reaction or process chamber for the CVD or sputtering process needs to be prepared. This reduces the productivity and as a result, the fabrication cost increases.
Accordingly, techniques that solve the problems of “corrosion of the transparent conductive layers” and “contact resistance increase” without the above-described first to third disadvantages is desired. Conventionally, various techniques have ever been developed and disclosed to meet the requirement.
For example, with the TFT-type LCD device disclosed in the Japanese Non-Examined Patent Publication No. 11-64887 published in 1999, a contact hole is formed in an insulating layer that covers an Al interconnection layer in such a way that the contact hole reaches the surface of the Al interconnection layer. On the insulating layer and the inner wall of the contact hole, an ITO layer (i.e., a transparent conductive layer) is formed. Moreover, a silicide layer is formed to intervene between the ITO layer and the Al interconnection layer at the bottom of the contact hole.
With the prior-art structure of the Publication No. 11-64887, because of the intervening silicide layer between the ITO layer and the Al interconnection layer, the contact-resistance increase due to direct contact of the ITO layer with the Al interconnection layer is suppressed. Moreover, since the silicide layer is formed only at the bottom of the contact hole of the Insulating layer, it is sufficient that the insulating layer covers the Al interconnection layer alone. This means that the step coverage of the insulating layer is improved. Moreover, since the depth of the contact hole is decreased by a value corresponding to the thickness of the silicide layer formed at the bottom of the said contact hole, the step coverage of the ITO layer is improved as well. Furthermore, since the interconnection lines are formed by only the Al interconnection layer, it is sufficient that a single etching process is carried out. This means that the patterning processes for the interconnection lines are easily conducted. (Refer to claim 1, paragraphs 0005 and 0006, and FIG. 1 of this Publication.)
The Japanese Non-Examined Patent Publication No. 2004-6936 published in 2004 discloses a TFT substrate. With this substrate, a gate electrode is formed by a first metal layer and a second metal layer (i.e., a capping layer) stacked on the first metal layer, where the first metal layer is formed on a transparent plate. A gate pad is formed by the second metal layer. An insulating layer is formed on the plate to selectively expose a part of the second metal layer. A patterned semiconductor layer is formed on the insulating layer to be superposed on the gate electrode. A source electrode and a drain electrode are formed on the semiconductor layer. A patterned protection layer is formed to have a contact hole exposing the drain electrode and a contact hole exposing the second metal layer of the gate pad. A first patterned pixel electrode is formed on the protection layer to be in contact with the drain electrode. A second patterned pixel electrode is formed on the protection layer to be in contact with the second metal layer of the gate pad. The first metal layer is made of, for example, Al or Al alloy. The second metal layer is made of, for example, Cr, Mo, Ta or Ti. The second pixel electrode is made of, for example, ITO. (Refer to claims 1 to 3, paragraphs 0012 to 0014, and FIG. 11 of this Publication.)
With the TFT substrate disclosed in the Publication No. 2004-6936, the gate electrode is formed to have a two-layer structure comprising an Al or Al alloy layer (i.e., the first metal layer) and a refractory metal layer made of Cr, Mo, Ta or Ti (i.e., the second metal layer). Therefore, cell reaction (i.e., electrochemical reaction) due to direct contact of the Al layer with the ITO layer is prevented and at the same time, the formation of hillocks is prevented. Moreover, an anodic oxidation process can be omitted with the second metal layer (i.e., the capping layer), and the insulating layer and the protection layer can be etched simultaneously and therefore, the count of necessary photolithography processes can be reduced. Furthermore, since the size of the first metal layer can be approximately the same as or larger than the second metal layer, the gate electrode has no undercut portion. Accordingly, the insulating characteristic deterioration of the insulating layer due to the step coverage degradation in the deposition process of the insulating layer after the formation of the gate electrode can be prevented.
However, the above-described techniques disclosed by the Japanese Publication Nos. 11-64887 and 2004-6936 have the following disadvantages.
Specifically, with the LCD device disclosed in the Publication No. 11-64887, after the formation of the Al layer, the silicide layer needs to be formed by a CVD or sputtering method necessitating the heating of the glass plate. Therefore, it is required to prepare a plasma-enhanced CVD apparatus or a sputtering apparatus and a sputtering target. Thus, a disadvantage that the fabrication cost of the LCD device increases by the cost for preparing the CVD apparatus or the sputtering apparatus and the target occurs. In addition, there is another disadvantage that the formation process of the silicide layer accelerates or promotes the formation of hillocks and/or voids of the Al layer due to thermal history.
With the above-described TFT substrate disclosed in the Publication No. 2004-6936, the gate electrode has the two-layer structure comprising the Al or Al alloy layer (i.e., the first metal layer) and the refractory metal layer made of Cr, Mo, Ta or Ti (i.e., the second metal layer). This means that the gate electrode line has the same two-layer structure as the gate electrode, because the gate electrode line is formed by the same patterned metal layers as the gate electrode. Therefore, there are the same disadvantages as those of the conventional interconnection structure shown in FIG. 1.